Simulation and Analysis of Graded-Channel Dual-Insulator Double-Gate Junction-less FET
In this paper, a Si/SiGe Graded-Channel (GC) Dual-Insulator (DI) Double-Gate (DG) Junction-less (JL) FET is presented. The proposed GC-DI-DG-JL FET is studied using 2D simulations to analyse the effect of gate metal workfunction (φm) variation in switching performance parameters. The increment in φm fully depletes the channel under OFF-state which improves the subthreshold characteristics of the proposed device. So that the proposed structure is benefited with the significant improvement in SS, DIBL and ION /IOF F by increasing φm. For an optimised value of φm, the GC-DI-DG-JL FET offers the SS of 70 mV /dec, Vt of 0.83 V , ION /IOF F of ∼ 10 12 and DIBL of 45 mV /V .