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Dual-Channel Trench-Gate (DCTG) Tunnel FET for Improved ON-current and subthreshold Swing


In this paper, a dual-channel trench-gate tunnel FET (DCTG-TFET) is proposed and investigated. The gate of DCTG-TFET is placed vertically in a trench to create two channels which carry drain current in parallel. The proposed device dimensions are optimized to reduce channel resistance and tunnelling width for appreciable increase in ON-state current (ION). The performance of DCTG-TFET is analysed using two-dimensional simulations in the device simulator (ATLAS). The proposed DCTGTFET provides one order of magnitude improvement in ION/IOF F current ratio and seventeen times reduction in subthreshold swing (SS) as compared to recently reported two-source-region (TRS) TFET structure.

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