Controlling Ambipolar Current in Ultra-thin SOI TFET using Back-Bias

In this paper, a 2-D TCAD based simulation study of back-bias in ultra-thin silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) is presented. The transfer characteristics of a conventional TFET called Back-Bias TFET (BB-TFET) depend on the back-bias and the oxide thickness below the TFET epitaxial layer. The back-bias affects the electric field at the source/channel and drain/channel junctions and hence both the ON-state current (ION ) and ambipolar current (IAMB) reduce with negative back-bias voltage. The reduction in ION is not desirable in a TFET and hence a modified TFET structure called Back-Bias Under-Drain TFET (BBUD-TFET) is proposed. In BBUD-TFET, the back bias is applied on a p−Si pocket placed under the drain region which is isolated with an ultra-thin oxide. The back bias in the proposed BBUD-TFET affects mainly the electric field at the drain/channel interface with a negligible impact on the source/channel interface. The BBUD-TFET structure is analyzed using SiO2 and HfO2 as gate oxides. In BBUD-TFET with HfO2 as the gate oxide, the back bias completely suppresses the ambipolar current without a reduction in ION. Further, the oxide thickness and back-bias voltage are optimized for the BBUD-TFET structure. In this study, 2-D TCAD simulations are carried out to investigate and analyze the performance of BB-TFET and BBUD-TFET.